1. Field of the Invention
The present invention relates to a method for writing into a semiconductor memory, and more particularly, it relates to a method for writing into a semiconductor memory which has a memory cell composed of a MOS transistor and an anti-fuse connected to the MOS transistor in series.
2. Related Art
In recent years, as shown in FIG. 2, a PROM memory cell M is known to include an n-channel MOS transistor 8 formed on a surface of a p-type semiconductor substrate 1 and an anti-fuse 7 connected to the MOS transistor 8 in series (e.g., "Dielectric Based Anti-fuse for Logic and Memory IC", IEDM 88, pp. 786-789). The anti-fuse 7 is formed by providing a thin insulating film 10 and an upper electrode 5 on a drain 3 of the MOS transistor 8, as shown in FIG. 3. Reference numeral 2 denotes a local oxidation film for isolating the memory cell M, while numeral 4 denotes a gate electrode. When some information is written in the memory cell M, first, a positive voltage is applied to the gate electrode 4 to turn the MOS transistor 8 on. For keeping the MOS transistor 8 in an ON state, a voltage V.sub.p which can break down the thin insulating film 10 (where the voltage Vp varies depending on the thickness of the thin insulating film 10, for example, if the thickness of the thin insulating film 10 is 50 .ANG., 10 to 15 V is necessary to breakdown the thin insulating film 10) is applied between the upper electrode 5 of the anti-fuse 7 and a source 6 of the MOS transistor 8 in such a direction that the upper electrode 5 turns positive while the source 6 turns negative with respect to electrode 5. In other words, voltage is applied through the MOS transistor 8 to the anti-fuse 7. Then, the insulating film 10 of the anti-fuse 7 is subjected to dielectric breakdown to make the anti-fuse 7 conductive. At this stage, conventionally, the writing operation is completed.
The basic cell construction includes a MOS transistor formed on the semiconductor substrate 1 and the anti-fuse 7 connected to the upper electrode 5 with the thin insulating film 10 as an intermediate covering the MOS transistor, wherein a portion of the thin insulating film 10 lying over the drain 3 is intended to become conductive. As a result, the thin insulating film 10 lying at that portion is made thinner than the thin insulating film lying in other portions. With such a design and with the MOS transistor turned ON, an application of a voltage on the upper electrode 5 breaks down only the insulating film 10 and forms conduction therethrough, wherein a portion of the upper electrode 5 lying over the portion of the insulating film 10 acts as the anti-fuse 7. Accordingly, other memory cells which were not subjected to such writing actions are left as each upper electrode 5 is not made conductive or insulated from the drain 3.
The dielectric breakdown of the anti-fuse 7 is caused by a current in the order of a few .mu. amperes (where this breakdown current changes depending on the characteristics of the MOS transistors). The electrical resistance of the anti-fuse 7 after the dielectric breakdown depends upon the current at the time of the dielectric breakdown. The electric resistance is reduced as the current is increased, while the electric resistance increases as the current decreases. When voltage is applied through the MOS transistor 8 to the anti-fuse 7 in a conventional manner, merely applying the voltage V.sub.p of the order of a few volts leads to a current limit, and the reduction in the electric resistance of the anti-fuse 7 may be limited. As a result, as shown in FIG. 1(a), there arises the problem that, upon the operation of the memory cell M, a voltage-current (V-I) characteristic is shown which curves in a low current range of 5 mA or below (a part shown by an arrow in the drawing), for expressing a non-linearity of the characteristic. The problem becomes more critical as miniaturization of the MOS transistor advances more and more. Since there is a limitation to the supply voltage, the voltage V.sub.p to be applied cannot be so large.
(An anti-fuse element includes that which is disclosed in the U.S. Pat. No. 4,899,205, for example.)